In memory products, especially for erasable programmable read only memory (EPROM) and flash memory, high voltage has to be applied to perform special applications such as programming and erasing. However, possible overshoot might occur when the high voltage is applied, and thus the high-voltage input pad should be capable of withstanding such overshoot. On the other hand, this high-voltage input pad should also have enough ESD performance to against to electrostatic discharge that is large-current and fast-transient event.
ESD protection scheme is proposed with two well-known mechanisms, transistor turn-on and transistor snapback, where the former is characterized in the threshold voltage for channel conduction of a protection transistor and the latter is characterized in the breakdown voltage of a snapback transistor. FIG. 1 is an NMOS transistor 10 connected to be a snapback device for high-voltage input pad in prior art ESD protection circuit, whose drain is connected to the protected high-voltage input pad, and source and gate are connected together to reference, such as ground. In this snapback device 10 two important factors related to ESD performance are triggering and holding voltages. Generally, the lower the triggering and holding voltages are, the better the ESD performance is. FIG. 2 shows the current-voltage (I-V) curve of the NMOS 10. For a typical example, the NMOS 10 with a nominal high voltage A (e.g., 12.5 V) may be impressed with an overshoot B (possible up to 16 V) larger than its triggering voltage C (e.g., 14 V) and thereby triggered into its snapback mode with a low holding voltage D (e.g., 8 V). In this circumstance, the high voltage on the input pad will charge the NMOS 10 till the triggering voltage C is reached and then the NMOS 10 snaps back to the holding voltage D. Even under normal operation, unfortunately, if the NMOS 10 is accidentally triggered, it will be damaged thermally due to its holding voltage D lower than the nominal high voltage A.
Therefore, it is desired an ESD protection apparatus and method with higher triggering and holding voltages under normal operation and lower triggering and holding voltages under ESD event.